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6A Low Quiescent Current High Efficiency Synchronous Buck Regulator
ISL8016
The ISL8016 is a high efficiency, monolithic, synchronous step-down DC/DC converter that can deliver up to 6A continuous output current from a 2.7V to 5.5V input supply. The output voltage is adjustable from 0.6V to VIN. With an adjustable current limit, reverse current protection, pre-bias start and over temperature protection the ISL8016 offers a highly robust power solution. It uses current control architecture to deliver fast transient response and excellent loop stability. The ISL8016 integrates a pair of low ON-resistance P-Channel and N-Channel internal MOSFETs to maximize efficiency and minimize external component count. 100% duty-cycle operation allows less than 200mV dropout at 6A output current. Adjustable frequency and synchronization allow the ISL8016 to be used in applications requiring low noise. Paralleling capability with phase interleaving allows the IC to support >6A output current while offering reduced input and output noise. The ISL8016 can be configured for discontinuous or forced continuous operation at light load. Forced continuous operation reduces noise and RF interference while discontinuous mode provides high efficiency by reducing switching losses at light loads. The ISL8016 is offered in a space saving 20 Ld 3x4 QFN lead free package with exposed pad lead frames for excellent thermal performance. The complete converter occupies less than 0.15in2 area. Various fixed output voltages are available upon request. See Ordering Information on page 2 for more detail.
Features
* High Efficiency Synchronous Buck Regulator with up to 97% Efficiency * 1% Reference Accuracy Over-Temperature/Load/Line * Fixed Output Voltage Option * 10% Output Voltage Margining * Adjustable Current Limit * Current Sharing Capable * Start-up with Pre-Biased Output * Internal Soft-Start - 1ms or Adjustable, Internal/External Compensation * Soft-Stop Output Discharge During Disabled * Adjustable Frequency from 500kHz to 4MHz - Default at 1MHz * External Synchronization up to 4MHz - Master to Slave Phase Shifting Capability * Peak current limiting, Hiccup Mode Short Circuit Protection and Over-Temperature Protection`
Applications
* DC/DC POL Modules * C/P, FPGA and DSP Power * Plug-in DC/DC Modules for Routers and Switchers * Portable Instruments * Test and Measurement Systems * Li-ion Battery Powered Devices
100
95
EFFICIENCY (%)
90
3.3VOUT PFM
85
3.3VOUT PWM
80
75
70 0.0
1.0
2.0
3.0 IOUT (A)
4.0
5.0
6.0
FIGURE 1. EFFICIENCY T = +25C VIN = 5V
March 31, 2011 FN7616.0
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 2011. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners.
ISL8016 Ordering Information
PART NUMBER (Notes 1, 2, 3) ISL8016IRAJZ ISL8016IR12Z ISL8016IR15Z ISL8016IR18Z ISL8016IR25Z ISL8016IR33Z NOTES: 1. Add "-T*" suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pbfree products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL8016. For more information on MSL please see techbrief TB363. PART MARKING 016A 016W 016B 016C 016F 016N OUTPUT VOLTAGE (V) Adjustable 1.2V 1.5V 1.8V 2.5V 3.3V TEMP. RANGE (C) -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 PACKAGE (Pb-Free) 20 Ld 3x4 QFN 20 Ld 3x4 QFN 20 Ld 3x4 QFN 20 Ld 3x4 QFN 20 Ld 3x4 QFN 20 Ld 3x4 QFN PKG. DWG. # L20.3x4 L20.3x4 L20.3x4 L20.3x4 L20.3x4 L20.3x4
Pin Configuration
ISL8016 (20 LD QFN) TOP VIEW
PGND PGND SGND VFB 17 16 15 14 PAD PHASE VIN VIN 4 5 6 7 VIN 8 PG 9 SYNCOUT 10 SYNCIN 13 12 11 VSET FS EN COMP SS ISET
20 PGND PHASE PHASE 1 2 3
19
18
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ISL8016 Pin Descriptions
PIN 1, 19, 20 2, 3, 4 5, 6, 7 8 9 SYMBOL PGND PHASE VIN PG SYNCOUT Power ground. Switching node connection. Connect to one terminal of the inductor. Input supply voltage. Connect two 22F ceramic capacitors to power ground. Power-good is an open-drain output. Use 10k to 100k pull-up resistor connected between VIN and PG. At power-up or EN HI, PG rising edge is delayed by 1ms from the output reaching regulation. This pin outputs a 250A current source that is turned on at the rising edge of the internal clock or SYNCIN. When SYNCOUT voltage reaches 1V, a reset circuit will activate and discharge SYNCOUT to 0V. SYNCOUT is held at 0V in PFM light load to reduce quiescent current. Mode Selection pin. Connect to logic high or input voltage VIN for PWM mode. Connect to logic low or ground for PFM mode. Connect to an external function generator for synchronization with the positive edge trigger. There is an internal 1M pull-down resistor to prevent an undefined logic state if SYNCIN is floating. Regulator enable pin. Enables the output when driven to high. Shuts down the chip and discharges the output capacitor when driven to low. There is an internal 1M pull-down resistor to prevent an undefined logic state in case of EN pin float. This pin sets the oscillator switching frequency, using a resistor, RFS, from the FS pin to GND. The frequency of operation may be programmed between 500kHz to 4MHz. The default frequency is 1MHz and configured for internal compensation if FS is connected to VIN. VSET is the output margining setting of the regulators. Connect to SGND for -10%, keep it floating for no margining, and connect to VIN for +10%. ISET is the peak output current limit and SKIP current limit setting of the regulators. Connect to SGND for 2A, to VIN for 4A, and keep it floating for 6A. SS is used to adjust the soft-start time. Set to SGND for internal 1ms rise time. Connect a capacitor from SS to SGND to adjust the soft-start time. Do not use more than 33nF per IC. The feedback network of the regulator, VFB, is the negative input to the transconductance error amplifier. COMP is the output of the amplifier if the FS resistor is used. If internal compensation is used (FS = VIN), the comp pin should be tied to SGND. The output voltage is set by an external resistor divider connected to VFB. With a properly selected divider, the output voltage can be set to any voltage between VIN and the 0.6V reference. While internal compensation offers a solution for many typical applications, an external compensation network may offer improved performance for some designs. In addition to regulation, VFB is also used to determine the state of PG. Short VFB to OUTPUT when using one of the available fixed VOUT options. Signal ground. The exposed pad must be connected to the SGND pin for proper electrical performance. Place as many vias as possible under the pad connecting to the system GND plane for optimal thermal performance. DESCRIPTION
10
SYNCIN
11
EN
12
FS
13 14 15 16, 17
VSET ISET SS COMP, VFB
18
SGND EPAD
3
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ISL8016 Typical Application Diagrams
INPUT 2.7V TO 5.5V VIN EN C1 2x22F R1 100k PG SYNCIN SYNCOUT VIN FS ISET VSET SGND VFB COMP SS * C3 is optional. Recommend putting a placeholder for it. Check loop analysis first before use. R3 100k PHASE L 1.0H C2 2x47F PGND R2 200k C3* 10pF OUTPUT 1.8V/6A
ISL8016
FIGURE 2. TYPICAL APPLICATION DIAGRAM - SINGLE CHIP 6A
TABLE 1. COMPONENT VALUE SELECTION VOUT C1 C2 (or C8) C3 (or C5) L1 (or L2) R2 (or R5) R3 (or R6) 0.8V 44F 2x47F 10pF 0.47~1H 33k 100k 1.2V 44F 2x47F 10pF 0.47~1H 100k 100k 1.5V 44F 2x47F 10pF 0.47~1H 150k 100k 1.8V 44F 2x47F 10pF 0.68~1.5H 200k 100k 2.5V 44F 2x47F 10pF 0.68~1.5H 316k 100k 3.3V 44F 2x47F 10pF 1~2.2H 450k 100k 3.6V 44F 2x47F 10pF 1~2.2H 500k 100k
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ISL8016
INPUT 2.7V TO 5.5V VIN EN R1 100k PG VIN PHASE L1 1.0H C2 2 x 47F OUTPUT 1.8V/12A
C1 47F
ISL8016 (MASTER) PGND
R3 100k
R2 200k
C3* 10pF
SYNCIN SYNCOUT FS SGND VFB
R4 196k
ISET VSET SS COMP C4 470pF R3 150k C5 10pF
C6 22nF
INPUT 2.7V TO 5.5V
VIN EN PG
PHASE
L2 1.0H C8 2 x 47F
C7 47F
ISL8016 (SLAVE)
PGND
SYNCOUT SYNCIN FS C13 100pF R5 249k ISET VSET SS SGND VFB
COMP * C3 is optional. Recommend putting a placeholder for it. Check loop analysis first before use.
FIGURE 3. TYPICAL APPLICATION DIAGRAM - MULTI CHIP CONFIGURATION 12A
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ISL8016 Block Diagram
COMP SS SHUTDOWN 55pF SHUTDOWN 168k + 250A OSCILLATOR P PHASE LS DRIVER N PGND VDD VIN FS SYNCIN SYNCOUT
Soft SOFT START
EN
VSET 3pF + VFB SLOPE Slope COMP 0.8V + OV
6k
0.85*VREF
+
PG
SGND
0.1V
6
+ -
BANDGAP
VREF
EAMP
+ COMP -
PWM/PFM LOGIC CONTROLLER PROTECTION HS DRIVER
+ CSA + OCP ISET THRESHOLD ISET
UV
+ SKIP -
1ms DELAY NEG CURRENT SENSING ZERO-CROSS SENSING SCP + SHUTDOWN 100
FIGURE 4. FUNCTIONAL BLOCK DIAGRAM
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ISL8016
Absolute Maximum Ratings (Reference to GND)
VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 5.8V (DC) or 7V (20ms) EN, FS, ISET, PG, SYNCOUT, SYNCIN VFB, VSET . . . . . . . -0.3V to VIN+0.3V PHASE . . . . . . . . . . . . -1.5V (100ns)/-0.3V (DC) to 6.5V (DC) or 7V (20ms) COMP, SS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.7V ESD Rating Human Body Model (Tested per JESD22-A114) . . . . . . . . . . . . . . . . . 3kV Machine Model (Tested per JESD22-A115). . . . . . . . . . . . . . . . . . . . 300V Charged Device Model (Tested per JESD22-C101E). . . . . . . . . . . . 1500V Latch Up (Tested per JESD-78A; Class 2, Level A) . . . . . .100mA @ +85C
Thermal Information
Thermal Resistance (Typical) JA (C/W) JC (C/W) 3x4 QFN Package (Notes 4, 5) . . . . . . . . . . 42 5 Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-55C to +125C Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
VIN Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V Load Current Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0A to 6A Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . -40C to +85C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379. 5. JC, "case temperature" location is at the center of the exposed metal pad on the package underside.
Analog Specifications Unless otherwise noted, all parameter limits are established over the recommended operating conditions and the typical specification are measured at the following conditions: TA = -40C to +85C, VIN = 3.6V, EN = VIN, unless otherwise noted. Typical
values are at TA = +25C. Boldface limits apply over the operating temperature range, -40C to +85C. PARAMETER SYMBOL TEST CONDITIONS MIN (Note 6) TYP MAX (Note 6) UNITS
INPUT SUPPLY
VIN Undervoltage Lockout Threshold VUVLO Rising, no load Falling, no load Quiescent Supply Current IVIN SYNCIN = GND, no load at the output SYNCIN = GND, no load at the output and no switches switching SYNCIN = VIN, FS = 1MHz, no load at the output Shut Down Supply Current ISD SYNCIN = GND, VIN = 5.5V, EN = low 2.2 2.5 2.4 70 70 8 5 90 15 7 2.7 V V A A mA A
OUTPUT REGULATION
Reference Voltage - ISL8016IRAJZ VREF VSET = VIN VSET = FLOAT VSET = SGND Output Voltage - ISL8016IR12Z Output Voltage - ISL8016IR15Z Output Voltage - ISL8016IR18Z Output Voltage - ISL8016IR25Z Output Voltage - ISL8016IR33Z Output Voltage Margining VVFB VVFB VVFB VVFB VVFB VVFB VSET = FLOAT VSET = FLOAT VSET = FLOAT VSET = FLOAT VSET = FLOAT VSET = VIN, Percent of OUTPUT changed VSET = SGND, Percent of OUTPUT changed VFB Bias Current - ISL8016IRAJZ Fixed Output VFB Bias Current - ISL8016IRXXZ Line Regulation Soft-Start Ramp Time Cycle Soft-Start Charging Current ISS IVFB IVFB VFB = 0.75V VSET = FLOAT, VFB = 10% above OUTPUT VIN = VO + 0.5V to 5.5V (minimal 2.7V) SS = SGND VSS = 0.1V 1.4 0.651 0.594 0.531 1.188 1.485 1.782 2.475 3.266 9.5 -10.5 0.660 0.600 0.540 1.200 1.500 1.800 2.500 3.300 10 -10 0.1 6 0.2 1 1.8 2.2 0.669 0.606 0.549 1.212 1.515 1.818 2.525 3.333 10.5 -9.5 V V V V V V V V % % A A %/V ms A
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ISL8016
Analog Specifications Unless otherwise noted, all parameter limits are established over the recommended operating conditions and the typical specification are measured at the following conditions: TA = -40C to +85C, VIN = 3.6V, EN = VIN, unless otherwise noted. Typical values are at TA = +25C. Boldface limits apply over the operating temperature range, -40C to +85C. (Continued)
PARAMETER SYMBOL TEST CONDITIONS MIN (Note 6) TYP MAX (Note 6) UNITS
OVERCURRENT PROTECTION
Current Limit Blanking Time Overcurrent and Auto Restart Period Positive Peak Current Limit tOCON tOCOFF IPLIMIT ISET = FLOAT ISET = VIN ISET = SGND Peak Skip Limit ISKIP ISET = FLOAT ISET = VIN ISET = SGND Zero Cross Threshold Negative Current Limit INLIMIT -300 -4.25 -3 7.7 5.5 3 1.6 1.0 17 8 9.5 6.5 4.0 2 1.35 0.85 300 -1.75 11.5 8.0 5 2.4 1.6 Clock pulses SS cycle A A A A A A mA A
COMPENSATION
Error Amplifier Trans-Conductance FS = VIN FS with Resistor Trans-Resistance RT 0.117 100 200 0.138 0.16 A/V A/V
PHASE
P-Channel MOSFET ON-Resistance VIN = 5V, IO = 200mA VIN = 2.7V, IO = 200mA N-Channel MOSFET ON-Resistance VIN = 5V, IO = 200mA VIN = 2.7V, IO = 200mA PHASE Maximum Duty Cycle PHASE Minimum On-Time SYNCIN = High 31 44 19 25 100 140 45 55 35 50 m m m m % ns
OSCILLATOR
Nominal Switching Frequency Fsw FS = VIN FS with RS = 402k FS with RS = 42.4k SYNCIN Logic Low to High Transition Range SYNCIN Hysteresis SYNCIN Logic Input Leakage Current SYNCOUT Charging Current ISO VIN = 3.6V PWM PFM SYNCOUT Voltage Low 210 800 450 3300 0.70 1000 525 3900 0.75 0.15 3.6 250 0 0.3 5 290 1200 600 4500 0.80 kHz kHz kHz V V A A A V
PG
Output Low Voltage Delay Time (Rising Edge) PG Pin Leakage Current OVP PG Rising Threshold UVP PG Rising Threshold 80 0.5 1 0.01 0.80 85 90 0.3 2 0.1 V ms A V %
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ISL8016
Analog Specifications Unless otherwise noted, all parameter limits are established over the recommended operating conditions and the typical specification are measured at the following conditions: TA = -40C to +85C, VIN = 3.6V, EN = VIN, unless otherwise noted. Typical values are at TA = +25C. Boldface limits apply over the operating temperature range, -40C to +85C. (Continued)
PARAMETER UVP PG Hysteresis PGOOD Delay Time (Falling Edge) SYMBOL TEST CONDITIONS MIN (Note 6) TYP 5 7 MAX (Note 6) UNITS % s
ISET, VSET
Logic Input Low Logic Input Float Logic Input High Logic Input Leakage Current 0.5 0.9 0.1 1 0.4 0.8 V V V A
EN
Logic Input Low Logic Input High EN Logic Input Leakage Current Thermal Shutdown Thermal Shutdown Hysteresis NOTE: 6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 0.9 0.1 150 25 1 0.4 V V A
C C
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ISL8016
EN = 3.3V, SYNCIN = VIN, L = 1.0H, C1 = 2x22F, C2 = 4x22F, VOUT = 1.8V, IOUT = 0A to 6A.
100 95
EFFICIENCY (%) EFFICIENCY (%)
Typical Operating Performance
Unless otherwise noted, operating conditions are: TA = +25C, VIN = 5V,
100 2.5VOUT 95 2.5VOUT 90 85 80 75 1.0 2.0 3.0 IOUT (A) 4.0 5.0 6.0 70 0.0 1.8VOUT 1.5VOUT 1.2VOUT
90 85 80 75 70 0.0
1.8VOUT
1.5VOUT 1.2VOUT
0.3
0.6
0.9 IOUT (A)
1.2
1.5
1.8
FIGURE 5. EFFICIENCY vs LOAD (1MHz 3.3VIN PWM)
FIGURE 6. EFFICIENCY vs LOAD (1MHz 3.3VIN PFM)
100 3.3VOUT 95
EFFICIENCY (%)
100 95
3.3VOUT
2.5VOUT 1.8VOUT 1.5VOUT 1.2VOUT
EFFICIENCY (%)
90 85 80 75 70 0.0
90 85 80 75
2.5VOUT
1.8VOUT
1.5VOUT
1.2VOUT
1.0
2.0
3.0 IOUT (A)
4.0
5.0
6.0
70 0.0
0.3
0.6
0.9 IOUT (A)
1.2
1.5
1.8
FIGURE 7. EFFICIENCY vs LOAD (1MHz 5VIN PWM)
FIGURE 8. EFFICIENCY vs LOAD (1MHz 5VIN PFM)
1.8 1.5 5VIN PWM MODE 1.2
VOUT (V) PD (W)
1.84 1.83 1.82 3.3VIN PWM MODE 3A LOAD 1.81 1.80 1.79 6A LOAD 0.0 1.0 2.0 3.0 IOUT (A) 4.0 5.0 6.0 1.78 2.5 3.0 3.5 4.0 VIN (V) 4.5 5.0 5.5 0A LOAD
0.9 0.6 0.3 0
FIGURE 9. POWER DISSIPATION vs LOAD (1MHz, VOUT = 1.8V)
FIGURE 10. VOUT REGULATION vs VIN (PWM VOUT = 1.8V)
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ISL8016
EN = 3.3V, SYNCIN = VIN, L = 1.0H, C1 = 2x22F, C2 = 4x22F, VOUT = 1.8V, IOUT = 0A to 6A. (Continued)
1.84 1.83 1.82
VOUT (V)
Typical Operating Performance
Unless otherwise noted, operating conditions are: TA = +25C, VIN = 5V,
1.24 1.23 1.22 3A LOAD 0A LOAD
VOUT (V)
3.3VIN PWM MODE
1.81 1.80 1.79
1.21 1.20 1.19 5VIN PWM MODE 5VIN PFM MODE
3.3VIN PFM MODE
6A LOAD 1.78 2.5 3.0 3.5 4.0 VIN (V) 4.5 5.0 5.5 1.18 0.0 1.0 2.0 3.0 IOUT (A) 4.0 5.0 6.0
FIGURE 11. VOUT REGULATION vs VIN (PFM VOUT = 1.8V)
FIGURE 12. VOUT REGULATION vs LOAD (1MHz, VOUT = 1.2V)
1.54 1.53 3.3VIN PWM MODE 1.52
VOUT (V) VOUT (V)
1.84 1.83 1.82 5VIN PWM MODE 3.3VIN PFM MODE 1.81 1.80 5VIN PFM MODE 1.79 4.0 5.0 6.0 1.78 0.0 5VIN PFM MODE 3.3VIN PWM MODE 5VIN PWM MODE
1.51 1.50 1.49 1.48 0.0
3.3VIN PFM MODE
1.0
2.0
3.0 IOUT (A)
1.0
2.0
3.0 IOUT (A)
4.0
5.0
6.0
FIGURE 13. VOUT REGULATION vs LOAD (1MHz, VOUT = 1.5V)
FIGURE 14. VOUT REGULATION vs LOAD (1MHz, VOUT = 1.8V)
2.54 2.53 3.3VIN PWM MODE 2.52
VOUT (V)
3.37 3.36 3.35 5VIN PWM MODE
VOUT (V)
5VIN PWM MODE
2.51 2.50 2.49 2.48 0.0
3.3VIN PFM MODE
3.34 3.33
5VIN PFM MODE
5VIN PFM MODE
3.32 3.31 0.0
1.0
2.0
3.0 IOUT (A)
4.0
5.0
6.0
1.0
2.0
3.0 IOUT (A)
4.0
5.0
6.0
FIGURE 15. VOUT REGULATION vs LOAD (1MHz, VOUT = 2.5V)
FIGURE 16. VOUT REGULATION vs LOAD (1MHz, VOUT = 3.3V)
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EN = 3.3V, SYNCIN = VIN, L = 1.0H, C1 = 2x22F, C2 = 4x22F, VOUT = 1.8V, IOUT = 0A to 6A. (Continued)
PHASE 2V/DIV PHASE 2V/DIV
Typical Operating Performance
Unless otherwise noted, operating conditions are: TA = +25C, VIN = 5V,
VOUT RIPPLE 20mV/DIV VOUT RIPPLE 20mV/DIV
IL 1A/DIV
IL 1A/DIV
FIGURE 17. STEADY STATE OPERATION AT NO LOAD (PWM)
FIGURE 18. STEADY STATE OPERATION AT NO LOAD (PFM)
PHASE 2V/DIV VOUT RIPPLE 50mV/DIV
IL 2A/DIV VOUT RIPPLE 20mV/DIV
IL 2A/DIV
FIGURE 19. STEADY STATE OPERATION WITH FULL LOAD
FIGURE 20. LOAD TRANSIENT (PWM)
VOUT RIPPLE 50mV/DIV EN 2V/DIV
IL 52A/DIV
VOUT 1V/DIV IL 1A/DIV
PG 5V/DIV
FIGURE 21. LOAD TRANSIENT (PFM)
FIGURE 22. SOFT-START WITH NO LOAD (PWM)
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EN = 3.3V, SYNCIN = VIN, L = 1.0H, C1 = 2x22F, C2 = 4x22F, VOUT = 1.8V, IOUT = 0A to 6A. (Continued)
Typical Operating Performance
Unless otherwise noted, operating conditions are: TA = +25C, VIN = 5V,
EN 2V/DIV EN 2V/DIV VOUT 1V/DIV VOUT 1V/DIV IL 1A/DIV IL 1A/DIV
PG 5V/DIV
PG 5V/DIV
FIGURE 23. SOFT-START AT NO LOAD (PFM)
FIGURE 24. SOFT-START WITH PRE-BIASED 1V
EN 2V/DIV
EN 2V/DIV
VOUT 1V/DIV
VOUT 1V/DIV IL 2A/DIV
IL 1A/DIV
PG 5V/DIV PG 5V/DIV
FIGURE 25. SOFT-START AT FULL LOAD
FIGURE 26. SOFT-DISCHARGE SHUTDOWN
PHASE 5V/DIV
PHASE 5V/DIV
VOUT RIPPLE 20mV/DIV
VOUT RIPPLE 20mV/DIV IL 2A/DIV
IL 0.5A/DIV
SYNC 5V/DIV
SYNC 5V/DIV
FIGURE 27. STEADY STATE OPERATION AT NO LOAD WITH FREQUENCY = 2MHz
FIGURE 28. STEADY STATE OPERATION AT FULL LOAD WITH FREQUENCY = 2MHz
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ISL8016
EN = 3.3V, SYNCIN = VIN, L = 1.0H, C1 = 2x22F, C2 = 4x22F, VOUT = 1.8V, IOUT = 0A to 6A. (Continued)
PHASE 5V/DIV
Typical Operating Performance
Unless otherwise noted, operating conditions are: TA = +25C, VIN = 5V,
PHASE 5V/DIV
VOUT RIPPLE 20mV/DIV
VOUT RIPPLE 20mV/DIV IL 2A/DIV
IL 0.2A/DIV
SYNC 5V/DIV
SYNC 5V/DIV
FIGURE 29. STEADY STATE OPERATION AT NO LOAD WITH FREQUENCY = 4MHz
FIGURE 30. STEADY STATE OPERATION AT FULL LOAD (PWM) WITH FREQUENCY = 4MHz
PHASE 5V/DIV PHASE 5V/DIV IL 2A/DIV VOUT 1V/DIV IL 5A/DIV VOUT 1V/DIV
PG 5V/DIV
PG 5V/DIV
FIGURE 31. OUTPUT SHORT CIRCUIT
FIGURE 32. OUTPUT SHORT CIRCUIT RECOVERY
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ISL8016 Theory of Operation
The ISL8016 is a step-down switching regulator optimized for battery-powered handheld applications. The regulator operates at 1MHz fixed default switching frequency when FS is connected to VIN. By connecting a resistor from FS to SGND, the operating frequency may be adjusted from 500kHz to 4MHz. Unless forced, PWM is chosen (SYNCIN pulled HI), the regulator will allow PFM operation and reduce switching frequency at light loading to maximize efficiency. In this condition, no load quiescent is typically 70A.
VEAMP VCSA DUTY CYCLE IL
PWM Control Scheme
Pulling the SYNCIN high (>0.8V) forces the converter into PWM mode, regardless of output current. The ISL8016 employs the current-mode pulse-width modulation (PWM) control scheme for fast transient response and pulse-by-pulse current limiting. Figure 4 shows the block diagram. The current loop consists of the oscillator, the PWM comparator, current sensing circuit and the slope compensation for the current loop stability. The slope compensation is 360mV/Ts. Current sense resistance, Rt, is typically 0.138V/A. The control reference for the current loop comes from the error amplifier's (EAMP) output. The PWM operation is initialized by the clock from the oscillator. The P-Channel MOSFET is turned on at the beginning of a PWM cycle and the current in the MOSFET starts to ramp up. When the sum of the current amplifier CSA and the slope compensation reaches the control reference of the current loop, the PWM comparator EAMP output sends a signal to the PWM logic to turn off the P-FET and turn on the N-Channel MOSFET. The N-FET stays on until the end of the PWM cycle. Figure 33 shows the typical operating waveforms during the PWM operation. The dotted lines illustrate the sum of the slope compensation ramp and the current-sense amplifier's CSA output. The output voltage is regulated by controlling the VEAMP voltage to the current loop. The bandgap circuit outputs a 0.6V reference voltage to the voltage loop. The feedback signal comes from the VFB pin. The soft-start block only affects the operation during the start-up and will be discussed separately. The error amplifier is a transconductance amplifier that converts the voltage error signal to a current output. The voltage loop is internally compensated with the 55pF and 168k RC network. The maximum EAMP voltage output is precisely clamped to 2.4V.
PWM 0.8V SYNCOUT PFM
VOUT
FIGURE 33. PWM OPERATION WAVEFORMS
SKIP Mode
Pulling the SYNCIN pin LO (<0.4V) forces the converter into PFM mode. The ISL8016 enters a pulse-skipping mode at light load to minimize the switching loss by reducing the switching frequency. Figure 34 illustrates the skip-mode operation. A zero-cross sensing circuit shown in Figure 4 monitors the N-FET current for zero crossing. When 8 consecutive cycles of the inductor current crossing zero are detected, the regulator enters the skip mode. During the eight detecting cycles, the current in the inductor is allowed to become negative. The counter is reset to zero when the current in any cycle does not cross zero. Once the skip mode is entered, the pulse modulation starts being controlled by the SKIP comparator shown in Figure 34. Each pulse cycle is still synchronized by the PWM clock. The P-FET is turned on at the clock's rising edge and turned off when the output is higher than 1.5% of the nominal regulation or when its current reaches the peak Skip current limit value. Then the inductor current is discharging to 0A and stays at zero. The internal clock is disabled. The output voltage reduces gradually due to the load current discharging the output capacitor. When the output voltage drops to the nominal voltage, the P-FET will be turned on again at the rising edge of the internal clock as it repeats the previous operations. The regulator resumes normal PWM mode operation when the output voltage drops 1.5% below the nominal voltage.
PWM
CLOCK 8 CYCLES IL 0 NOMINAL +1.5% VOUT NOMINAL NOMINAL -1.5% PFM CURRENT LIMIT LOAD CURRENT
FIGURE 34. SKIP MODE OPERATION WAVEFORMS
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ISL8016
Frequency Adjust
The frequency of operation is fixed at 1MHz and internal compensation when FS is tied to VIN. Adjustable frequency ranges from 500kHz to 4MHz via a simple resistor connecting FS to SGND according to Equation 1:
220 10 3 R T [ k ] = ----------------------------- - 14 f OSC [ kHz ] (EQ. 1)
PHASE1 CLOCK1
SYNCIN_S SYNCOUT_M w/Cap
0.75V
0.8V
Figure 35 is a graph of the measured Frequency vs RT for a VIN of 2.7V and 5.5V.
4200 3500 2800 FS (kHz) 2100 1400 VIN = 2.7V 700 0 VIN = 5.5V
20nsDELAY PHASE2
FIGURE 36. SYNCHRONIZATION WAVEFORMS
Figure 37 is a graph of the Master to Slave phase shift vs SYNCOUT capacitance for 1MHz switching operation.
300 250 PHASE SHIFT () 200 150 100 50 0 PHASE SHIFT CALCULATION 0 40 80 120 C13 (pF) 160 200 240 PHASE SHIFT MEASUREMENT
0
70
140
210 RTs (k)
280
350
420
FIGURE 35. FREQUENCY vs RTs
Synchronization Control
The ISL8016 can be synchronized from 500kHz to 4MHz by an external signal applied to the SYNCIN pin. SYNCIN frequency should be greater than 50% of internal clock frequency. The rising edge on the SYNCIN triggers the rising edge of the PHASE pulse. Make sure that the minimum on time of the PHASE node is greater than 140ns. SYNCOUT is a 250A current pulse signal output trigger on by rising edge of the clock or SYNCIN signal (whichever is greater in frequency) to dive other ISL8016 and avoid system's beat frequencies effect. See Figure 36 for more detail. The current pulse is terminated and SYNCOUT is discharged to 0V after 0.8V threshold is reached. SYNCOUT is 0V if the regulator operates at light PFM load. To implement time shifting between the master circuit to the slave, it is recommended to add a capacitor, C13 as shown in Figure 3. The time delay from SYNCOUT_Master to SYNCIN_Slave as shown in Figure 3 is calculated in pF using Equation 2:
C 13 ( pF ) = 0.333 ( t - 20 ) ( ns ) (EQ. 2)
FIGURE 37. PHASE SHIFT vs CAPACITANCE
Overcurrent Protection
The overcurrent protection is realized by monitoring the CSA output with the OCP comparator, as shown in Figure 4. The current sensing circuit has a gain of 138mV/A, from the P-FET current to the CSA output. When the CSA output reaches a threshold set by ISET, the OCP comparator is tripped to turn off the P-FET immediately. See "Analog Specifications" on page 7 of the OCP threshold for various ISET configurations. The overcurrent function protects the switching converter from a shorted output by monitoring the current flowing through the upper MOSFET. Upon detection of overcurrent condition, the upper MOSFET will be immediately turned off and will not be turned on again until the next switching cycle. Upon detection of the initial overcurrent condition, the overcurrent fault counter is set to 1. If, on the subsequent cycle, another overcurrent condition is detected, the OC fault counter will be incremented. If there are 17 sequential OC fault detections, the regulator will be shut down under an overcurrent fault condition. An overcurrent fault condition will result in the regulator attempting to restart in a hiccup mode within the delay of eight soft-start periods. At the end of the eight soft-start wait period, the fault counters are reset and soft-start is attempted again. If the overcurrent condition goes away during the delay of eight soft-start periods, the output will resume back into regulation point after hiccup mode expires.
FN7616.0 March 31, 2011
Where t is the desired time shift between the master and the slave circuits in ns. Care must be taken to include PCB parasitic capacitance of ~3pF to 10pF. The maximum should be limited to 1/Fs-100ns to insure that SYNCOUT has enough time to discharge before the next cycle starts.
16
ISL8016
Negative Current Protection
Similar to the overcurrent, the negative current protection is realized by monitoring the current across the low-side N-FET, as shown in Figure 4. When the valley point of the inductor current reaches -3A for 4 consecutive cycles, both P-FET and N-FET are off. The 100 in parallel to the N-FET will activate discharging the output into regulation. The control will begin to switch when output is within regulation. The regulator will be in PFM for 20s before switching to PWM if necessary. Figure 38 is a comparison between measured and calculated output soft-start time versus Css capacitance.
18 15 12 VSS (ms) 9 6 3 0 SS (ms) CALCULATION SS (ms) MEASUREMENT
PG
PG is an open-drain output of a window comparator that continuously monitors the buck regulator output voltage. PG is actively held low when EN is low and during the buck regulator soft-start period. After 1ms delay of the soft-start period, PG becomes high impedance as long as the output voltage is within nominal regulation voltage set by VFB. When VFB drops 15% below or raises 0.8V above the nominal regulation voltage, the ISL8016 pulls PG low. Any fault condition forces PG low until the fault condition is cleared by attempts to soft-start. For logic level output voltages, connect an external pull-up resistor, R1, between PG and VIN. A 100k resistor works well in most applications.
0
8
16
24 CSS (nF)
32
40
48
FIGURE 38. SOFT-START TIME vs CSS
Enable
The enable (EN) input allows the user to control the turning on or off of the regulator for purposes such as power-up sequencing. When the regulator is enabled, there is typically a 600s delay for waking up the bandgap reference and then the soft start-up begins.
UVLO
When the input voltage is below the undervoltage lock-out (UVLO) threshold, the regulator is disabled.
Soft Start-Up
The soft start-up reduces the in-rush current during the start-up. The soft-start block outputs a ramp reference to the input of the error amplifier. This voltage ramp limits the inductor current as well as the output voltage speed so that the output voltage rises in a controlled fashion. When VFB is less than 0.1V at the beginning of the soft-start, the switching frequency is reduced to 200kHz so that the output can start-up smoothly at light load condition. During soft-start, the IC operates in the SKIP mode to support pre-biased output condition. Tie SS to SGND for an internal soft-start of approximately 1ms. Connect a capacitor from SS to SGND to adjust the soft-start time. This capacitor, along with an internal 1.6A current source sets the soft-start interval of the converter, tSS.
C SS [ F ] = 3.33 t SS [ s ] (EQ. 3)
Discharge Mode (Soft-Stop)
When a transition to shutdown mode occurs or the VIN UVLO is set, the outputs discharge to GND through an internal 100 switch. The discharge mode is disabled if SS is tied to an external capacitor.
Power MOSFETs
The power MOSFETs are optimized for best efficiency. The ON-resistance for the P-FET is typically 30m and the ON-resistance for the N-FET is typically 20m.
100% Duty Cycle
The ISL8016 features 100% duty cycle operation to maximize the battery life. When the battery voltage drops to a level that the ISL8016 can no longer maintain the regulation at the output, the regulator completely turns on the P-FET. The maximum dropout voltage under the 100% duty-cycle operation is the product of the load current and the ON-resistance of the P-FET.
CSS must be less than 33nF to insure proper soft-start reset after fault condition.
Thermal Shutdown
The ISL8016 has built-in thermal protection. When the internal temperature reaches +150C, the regulator is completely shut down. As the temperature drops to +125C, the ISL8016 resumes operation by stepping through the soft-start.
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ISL8016 Applications Information
Output Inductor and Capacitor Selection
To consider steady state and transient operations, ISL8016 typically uses a 1.0H output inductor. The higher or lower inductor value can be used to optimize the total converter system performance. For example, for higher output voltage 3.3V application, in order to decrease the inductor current ripple and output voltage ripple, the output inductor value can be increased. It is recommended to set the ripple inductor current approximately 30% of the maximum output current for optimized performance. The inductor ripple current can be expressed as shown in Equation 4:
VO V O * 1 - ------- V IN I = ----------------------------------L * fS
VOUT (V) 3.0 2.5 VIN = 5V 2.0 1.5 1.0 VIN = 3.3V 0.5 0.0 0.5
1.0
1.5
2.0 2.5 FREQUENCY (MHz)
3.0
3.5
4.0
(EQ. 4)
FIGURE 39. MINIMUM VOUT vs FREQUENCY
The inductor's saturation current rating needs to be at least larger than the peak current. The ISL8016 protects the typical peak current of 9A. The saturation current needs be over 12A for maximum output current application. The ISL8016 uses an internal compensation network and the output capacitor value is dependent on the output voltage. The ceramic capacitor is recommended to be X5R or X7R. In Table 1, the minimum output capacitor value is given for the different output voltages to make sure that the whole converter system is stable. Additional output capacitance may be added for improved transient response.
Input Capacitor Selection
The main functions for the input capacitor are to provide decoupling of the parasitic inductance and to provide filtering function to prevent the switching current flowing back to the battery rail. At least two 22F X5R or X7R ceramic capacitors are a good starting point for the input capacitor selection.
Loop Compensation Design
When there is an external resistor connected from FS to SGND, the COMP pin is active for external loop compensation. The ISL8016 uses constant frequency peak current mode control architecture to achieve fast loop transient response. An accurate current sensing pilot device in parallel with the upper MOSFET is used for peak current control signal and overcurrent protection. The inductor is not considered as a state variable since its peak current is constant, and the system becomes single order system. It is much easier to design a type II compensator to stabilize the loop than to implement voltage mode control. Peak current mode control has inherent input voltage feed-forward function to achieve good line regulation. Figure 40 shows the small signal model of the synchronous buck regulator.
^ IIN ^ VIN + ^ ILd 1:D ^ IL LP RLP ^ vo
Output Voltage Selection
The output voltage of the regulator can be programmed via an external resistor divider that is used to scale the output voltage relative to the internal reference voltage and feed it back to the inverting input of the error amplifier (refer to Figure 2). The output voltage programming resistor, R2, will depend on the value chosen for the feedback resistor and the desired output voltage of the regulator. The value for the feedback resistor is typically between 10k and 100k, as shown in Equation 5.
VO R 2 = R 3 ---------- - 1 VFB (EQ. 5)
^ VINd RT Rc Ro Co
+
If the output voltage desired is 0.6V, then R3 is left unpopulated and R2 is shorted. There is a leakage current from VIN to PHASE. It is recommended to preload the output with 10A minimum. Capacitance, C3, maybe added to improve transient performance. A good starting point for C3 can be determined by choosing a value that provides an 80kHz corner frequency with R2. VSET marginally adjusts VFB according to the "Analog Specifications" on page 7. Figure 39 is the recommended minimum output voltage setting vs operational frequency in order to avoid the minimum On-Time specification.
^ d Fm
Ti(S) K
+
He(S) ^ VCOMP -Av(S)
TV(S)
FIGURE 40. SMALL SIGNAL MODEL OF SYNCHRONOUS BUCK REGULATOR
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ISL8016
PWM COMPARATOR GAIN Fm:
The PWM comparator gain Fm for peak current mode control is given by Equation 6:
1 d F m = --------------- = ---------------------------- ( S e + S n )T s v comp (EQ. 6) S 1 + ----------V FB R o + R LP esr A v ( S ) 1 L v ( S ) = -------- ---------------------- --------------------- -------------- , p ------------Rt Vo Ro Co S- H ( S ) 1 + ------ e p (EQ. 14)
Where, Se is the slew rate of the slope compensation and Sn is given by Equation 7:
V in - V o S n = R t ------------------L
P
From Equation 14, it is shown that the system is a single order system, which has a single pole located at p before the half switching frequency. Therefore, a simple type II compensator can be easily used to stabilize the system.
Vo
(EQ. 7)
Where Rt is trans-resistance, which is the gain of the current amplifier.
R2
C3 V FB GM + R6 C6 VCOMP
CURRENT SAMPLING TRANSFER FUNCTION He(S):
In current loop, the current signal is sampled every switching cycle. It has the following transfer function:
S S H e ( S ) = ------ + ------------- + 1 2 Q nn n where Qn and n are given by Q n = - -- , n = f s 2
2
R3
VREF
(EQ. 8)
C7
Power Stage Transfer Functions
Transfer function F1(S) from control to output voltage is:
S1 + ---------- esr vo F 1 ( S ) = ----- = V in ------------------------------------ 2 d S S ------ + ------------- + 1 2 Q op o Co 1 1 Where esr = ------------ ,Q p R o ----- , o = ---------------Rc Co LP LP Co (EQ. 9) FIGURE 41. TYPE II COMPENSATOR
Figure 41 shows the type II compensator and its transfer function is expressed as follows:
S S 1 + ------------ 1 + ------------ cz1 cz2 v comp GM A v ( S ) = --------------- = ------------------- ------------------------------------------------------- C6 + C7 S v FB S 1 + --------- cp 1 1 6 7 Where cz1 = ------------- , cz2 = ------------- , cp = -------------------R6 C6 R2 C3 C +C R6 C6 C7 (EQ. 15)
Transfer function F2(S) from control to inductor current is given by Equation 10:
S 1 + ---- V in z Io F 2 ( S ) = --- = ---------------------- ------------------------------------ R o + R LP 2 d S - ------------S------ + +1 2 Q op o (EQ. 10)
Compensator design goal: High DC gain
11 Loop bandwidth fc: -- to ------ f s 4 10 Gain margin: >10dB
where z = ------------- . Ro Co Current loop gain Ti(S) is expressed as Equation 11:
T i ( S ) = R t F m F 2 ( S )H e ( S ) (EQ. 11)
1
Phase margin: 40 The compensator design procedure is as follows: Put compensator zero cz1 = ( 1to3 ) ------------RC
(EQ. 12) 1
oo
The voltage loop gain with open current loop is:
T v ( S ) = KF m F 1 ( S )A v ( S )
The Voltage loop gain with current loop closed is given by Equation 13:
Tv ( S ) L v ( S ) = ---------------------1 + Ti ( S ) (EQ. 13)
Put one compensator pole at zero frequency to achieve high DC gain, and put another compensator pole at either ESR zero frequency or half switching frequency, whichever is lower. An optional zero can boost the phase margin. CZ2 is a zero due to R2 and C3. Put compensator zero cz2 = ( 5to8 ) ------------RC
1
oo
V FB K = -------- , V FB Vo Where is the feedback voltage of the voltage
The loop gain Tv (S) at cross over frequency of fc has unity gain. Therefore, the compensator resistance R6 is determined by:
2f c V o C o R t R 6 = ------------------------------GM V FB (EQ. 16)
error amplifier. If Ti(S)>>1, then Equation 13 can be simplified by Equation 14:
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ISL8016
where GM is the sum of the trans-conductance, gm, of the voltage error amplifier in each phase. Compensator capacitor C6 is then given by:
1 1 C 6 = ---------------- ,C 7 = -----------------------R 6 cz 2R 6 f esr (EQ. 17)
PCB Layout Recommendation
The PCB layout is a very important converter design step to make sure the designed converter works well. For ISL8016, the power loop is composed of the output inductor L's, the output capacitor COUT, the PHASE's pins, and the PGND pin. It is necessary to make the power loop as small as possible and the connecting traces among them should be direct, short and wide. The switching node of the converter, the PHASE pins, and the traces connected to the node are very noisy, so keep the voltage feedback trace away from these noisy traces. The input capacitor should be placed as close as possible to the VIN pin , and the ground of the input and output capacitors should be connected as close as possible. The heat of the IC is mainly dissipated through the thermal pad. Maximizing the copper area connected to the thermal pad is preferable. In addition, a solid ground plane is helpful for better EMI performance. It is recommended to add at least 5 vias ground connection within the pad for the best thermal relief.
Example: VIN = 5V, Vo = 2.5V, Io = 6A, fs = 1MHz, Co = 44F/3m, L = 1H, GM = 100s, Rt = 0.25V/A, VFB = 0.6V, Se = 0.15V/s, Sn = 2.55x105V/s, fc = 100kHz, then compensator resistance R6 = 120k. Put the compensator zero at 1.5kHz (~1.5x CoRo), and put the compensator pole at ESR zero which is 390kHz. The compensator capacitors are: C6 = 220pF, C7 = 3pF (there is approximately 3pF parasitic capacitance from VCOMP to GND; therefore, C7 optional). Figure 42 shows the simulated loop gain response. It is shown that it has 95kHz loop bandwidth with 79 phase margin and at least 10dB gain margin.
60 45 30 15 0 -15 -30 100 180 150 120 PHASE LOOP () 90 60 30 0
GAIN LOOP (dB)
1k
10k
100k
1M
100
1k
10k
100k
1M
FIGURE 42. SIMULATED LOOP GAIN
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ISL8016 Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev.
DATE 3/31/11 REVISION FN7616.0 Initial Release. CHANGE
Products
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ISL8016
Package Outline Drawing
L20.3x4
20 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 1, 3/10
3.00 A B
4
0.10 M C A B 0.05 M C 20X 0.25
+0.05 -0.07
16X 0.50 20 1 6 PIN 1 INDEX AREA (C 0.40)
A
6 PIN 1 INDEX AREA 16
17
4.00 2.65
+0.10 -0.15
11 0.15 (4X) 10 7
+0.10 -0.15
6
A
TOP VIEW
VIEW "A-A"
1.65 20x 0.400.10
BOTTOM VIEW
SEE DETAIL "X"
0.9 0.10
0.10 C
C
SEATING PLANE 0.08 C (16 x 0.50) (2.65) (3.80) (20 x 0.25) C 0.2 REF 5
SIDE VIEW
(20 x 0.60) (1.65) (2.80)
0.00 MIN. 0.05 MAX.
DETAIL "X" TYPICAL RECOMMENDED LAND PATTERN
NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal 0.05 4. Dimension applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 indentifier may be either a mold or mark feature.
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